1. Field
Aspects of the present disclosure relate generally to memory, and more particularly, to a receiver architecture for memory reads.
2. Background
A chip may include a memory interface for interfacing circuits (e.g., a memory controller) on the chip with an external memory device, such as a dynamic random access memory (DRAM). To read data from the memory device, the memory interface receives a plurality of data signals in parallel from the memory device over a plurality of I/O channels. The memory interface may also receive a data strobe signal from the memory device, and use the received data strobe signal to time the capture of data bits from the received data signals. Interfacing with a high-speed DRAM (e.g., a double data rate (DDR) synchronous DRAM (SDRAM)) can be extremely challenging because the high speeds translate into tight timing constraints that need to be met by the memory interface in order to properly read data from the DRAM.